1. Field of the Invention
The present invention relates to a method of fabricating a non-volatile memory device, and more particularly, to a method of fabricating a floating gate having a high capacitance.
2. Description of the Related Art
In volatile semiconductor memory devices, stored data is lost when the supply of power is stopped. On the other hand, in non-volatile semiconductor memory devices, stored data is not lost even if the supply of power is stopped. Recently, flash memories, a type of non-volatile memory, are being widely used as storage devices for products such as personal computers or still cameras. A non-volatile memory device can semi-permanently store desired information by applying a voltage to a control gate, trapping electrons from a semiconductor substrate, and storing the trapped electrons in a floating gate. A high coupling ratio is required for such a non-volatile memory device. The coupling ratio is determined by the ability to store charge in a floating gate, that is, by a capacitance. In order to increase the capacitance induced between the control gate and the floating gate, there have been proposed methods of (1) forming a dielectric film of an ONO structure on the floating gate, (2) forming hemispherical grains on the surface of the floating gate, and (3) enlarging the surface of the floating gate as much as possible. When the method (3) is used, decreasing the spacing between adjacent floating gates to within a predetermined range is significantly restricted due to limits of current photolithographic techniques.
In FIG. 1, which shows the layout of a floating gate pattern in a conventional non-volatile memory device, reference numeral 100 denotes an active region, and reference numeral 110 denotes a floating gate pattern on the active region 100. The spacing or gap between floating gate patterns is indicated by reference character (a) shown in FIG. 2.
In FIG. 2, which shows the cross sectional view of the non-volatile memory device taken along line A-Axe2x80x2, of FIG. 1, isolation regions 202 are formed on a semiconductor substrate 200. Floating gates 210 are formed on predetermined areas of the semiconductor substrate 200. Referring to FIG. 2, it becomes evident that a method of increasing the width (b) of a floating gate to enlarge the surface of the floating gate is restricted by the spacing (a) between adjacent floating gates.
A method of forming a gate electrode which is used to reduce the spacing between floating gates in a conventional non-volatile memory device, will now be described with reference to FIGS. 3A through 3E.
Referring to FIG. 3A, a tunnel oxide layer 320, a first polycrystalline silicon layer 330, a silicon nitride layer 340, and a second polycrystalline silicon layer 350 are sequentially formed on the surface of a semiconductor substrate 300 having isolation regions 310 formed therein.
Referring to FIG. 3B, the silicon nitride layer 340 and the second polycrystalline silicon layer 350 are etched by photolithography, thereby forming silicon nitride layer patterns 342 and second polycrystalline silicon layer patterns 352. A silicon nitride layer is deposited on the entire surface of the resultant structure, and then anisotropically etched, thereby forming sidewall spacers 360 on the sidewalls of the silicon nitride layer patterns 342 and the second polycrystalline silicon layer patterns 352.
Referring to FIGS. 3C and 3D, which show forming floating gates, the first polycrystalline silicon layer 330 and the second polycrystalline layer pattern 352 are etched using the sidewall spacers 360 as a mask. Consequently, the surfaces of the isolation regions 310 are exposed, so that the first polycrystalline silicon layer 330 is patterned. Also, the second polycrystalline silicon layer patterns 352 are removed. Next, the silicon nitride layer patterns 342 and the sidewall spacers 360 are removed using phosphoric acid, thereby completing the formation of the floating gates 332. Reference character (a) of FIG. 3D denotes the spacing between adjacent floating gates 332. In the above, when the silicon nitride layer patterns 342 and the sidewall spacers 360 are removed using phosphoric acid, a portion of the floating gates 332, which is exposed to the phosphoric acid used as an etching solution, may be damaged.
Referring to FIG. 3E showing a step of forming a dielectric layer and a control gate, first, a dielectric layer 370 is formed on the semiconductor substrate 300 on which the floating gates 332 have been formed. A conductive material is deposited on the dielectric layer 370, and then patterned, thereby forming a control gate 380.
When a gate electrode is formed by the above-described method, the spacing between floating gates is restricted by limits of a photolithographic process for forming floating gate patterns. Thus, a method of forming a floating gate having an enlarged surface to increase a capacitance is strongly affected by the limits of the photolithographic process. That is, when floating gate patterns are formed by photolithography, light diffraction or the like makes it difficult to form floating gate patterns which are narrowly spaced apart from each other.
In order to solve this problem, U.S. Pat. No. 5,376,227 discloses a multilevel resist process. In this method, finer patterns can be formed by etching using multilevel resist patterns during photolithography. However, this method is very complicated since multilevel resist layers must be formed. Also, it is still difficult to form floating gates having a spacing of 0.1 xcexcm or less therebetween using this method.
The present invention provides a method of forming an floating gate having an enlarged surface by minimizing the spacing between floating gates by overcoming the limitations of photolithography.
Also, the present invention provides a method of forming a floating gate without damage to the floating gate.
According to an embodiment of the present invention, in a method of fabricating floating gates in a semiconductor device, first, a tunnel oxide layer, a polycrystalline silicon layer, an interlayer oxide layer, and a silicon nitride layer are sequentially formed on a semiconductor substrate having isolation regions. A plurality of silicon nitride layer patterns, which are separated from each other by predetermined distances, are formed by etching the silicon nitride layer. The surface of the polycrystalline silicon layer is exposed by etching the interlayer oxide layer using the silicon nitride layer patterns as an etch mask, thereby forming a plurality of interlayer oxide layer patterns. Sidewall spacers are formed on the sidewalls of the silicon nitride layer patterns and the interlayer oxide layer patterns. A mask layer is formed on a region of the exposed surface of the polycrystalline silicon layer. The silicon nitride layer patterns and the sidewall spacers are removed. The isolation regions are exposed by etching the polycrystalline silicon layer using the interlayer oxide layer patterns and the mask layer as an etch mask.
Preferably, the widths of the silicon nitride layer patterns are the same as the widths of the floating gates, and the spacing between adjacent silicon nitride layer patterns is greater than the width of a silicon nitride layer pattern. Also, preferably, the spacing between adjacent floating gates is determined by the width of the sidewall spacer. It is preferable that the spacing between adjacent floating gates is 0.1 xcexcm or less. Preferably, the mask layer is a thermal oxide layer formed by thermally oxidizing the region of the exposed surface of the polycrystalline silicon layer. Forming the sidewalls comprises forming a silicon nitride layer on the semiconductor substrate on which the silicon nitride layer patterns have been formed, and anisotropically etching the silicon nitride layer. It is preferable that the silicon nitride layer is formed to a thickness that is the same as the width of each of the sidewall spacers intended to be formed.
According to another embodiment of the present invention, in a method of fabricating floating gates in a semiconductor device, first, a tunnel oxide layer, a first polycrystalline silicon layer, a lower oxide layer, a second polycrystalline silicon layer, an upper oxide layer, and a silicon nitride layer are sequentially formed on a semiconductor substrate having isolation regions. A plurality of silicon nitride layer patterns, which are separated from each other by predetermined distances, are formed by etching the silicon nitride layer. The first surface of the second polycrystalline silicon layer is exposed by etching the upper oxide layer using the silicon nitride layer patterns as an etch mask. A plurality of upper oxide layer patterns are formed. Sidewall spacers are formed on the sidewalls of the silicon nitride layer patterns and the upper oxide layer patterns. A mask layer is formed on the lower oxide layer by thermally oxidizing a region of the first exposed surface of the second polycrystalline silicon layer. The silicon nitride layer patterns and the sidewall spacers are removed. The second exposed surface of the second polycrystalline silicon layer is etched, using the mask layer and the upper oxide layer patterns as an etch mark thereby exposing a surface of the lower oxide layer. Lower oxide layer patterns are formed by etching the mask layer, the upper oxide layer patterns, and the exposed surface of the lower oxide layer. The second polycrystalline silicon layer is removed. The surfaces of the isolation regions are exposed by etching the first polycrystalline silicon layer using the lower oxide layer patterns as an etch mask. The lower oxide layer patterns are removed.
Preferably, the widths of the silicon nitride layer patterns are the same as the widths of the floating gates, and the spacing between adjacent silicon nitride layer patterns is greater than the width of the silicon nitride layer pattern. Also, it is preferable that the spacing between adjacent floating gates is determined by the width of each of the sidewall spacers.
In accordance with still another embodiment of the present invention, in a method of fabricating floating gates in a semiconductor device, first, a tunnel oxide layer, a polycrystalline silicon layer, an interlayer oxide layer, and a silicon nitride layer are sequentially formed on a semiconductor substrate having isolation regions. A plurality of silicon nitride layer patterns, which are separated from each other by predetermined distances, are formed by etching the silicon nitride layer. The surface of the polycrystalline silicon layer is exposed by etching the interlayer oxide layer using the silicon nitride layer patterns as an etch mask, thereby forming a plurality of interlayer oxide layer patterns. Sidewall spacers are formed on the sidewalls of the silicon nitride layer patterns and the interlayer oxide layer patterns. A mask layer is formed on the entire surface of the resultant structure. The mask layer is planarized so that the silicon nitride layer patterns are at least partially removed and the sidewall spacers are exposed. The silicon nitride layer patterns and the sidewall spacers are removed. The isolation regions are exposed by etching the polycrystalline silicon layer using the interlayer oxide layer patterns and the mask layer as an etch mask.
Preferably, the widths of the silicon nitride layer patterns are the same as the widths of the floating gates, and the spacing between adjacent silicon nitride layer patterns is greater than the width of the silicon nitride layer pattern. Also, it is preferable that the spacing between adjacent floating gates is substantially equal to the width of each of the sidewall spacers. Preferably, the mask layer is an oxide layer formed by chemical vapor deposition (CVD).
According to the present invention, the spacing between floating gates is determined by the width of a sidewall spacer, so that fine floating gate patterns can be formed at narrower spacings overcoming the limits of photolithography. Also, the surfaces of floating gates are not exposed to an etching solution containing phosphoric acid or the like, such that damage to the surfaces of the floating gates is prevented to thus reduce current leakage.